The development of complicated physical systems often requires powerful numerical simulation programs. For example, circuit simulation is now an essential part in the design flow of integrated circuits. It helps circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as, SPICE2 or SPICE3, also developed at UC Berkeley; HSPICE, developed by Meta-software and now owned by Synopsys; PSPICE, developed by Micro-Sim; and SPECTRE, developed by Cadence. The SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE.
An electronic circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc. SPICE usually handles a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and solving the nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrix stamps.
A device model for modeling a circuit element, such as the BSIM4 model for modeling MOSFET devices developed by UC Berkeley, typically includes model equations and a set of model parameters to mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . , Vn, t) for i=1, . . . , n,where Ii represents the current entering terminal i, Vj (j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground, and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
      G    ⁡          (                                    V                          1              ,                                ⁢          …                ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  f                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋰                                ⋮                                                                              ∂                                  f                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  f                  n                                                            ∂                                  V                  n                                                                        )        .  To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:□Qi=qi(V1, . . . , Vn, t) for i=1, . . . , n.where Qi represents the represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
      C    ⁡          (                                    V                          1              ,                                ⁢          …                ⁢                                  ,                  V          n                ,        t            )        :=            (                                                                  ∂                                  q                  1                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  1                                                            ∂                                  V                  n                                                                                          ⋮                                ⋰                                ⋮                                                                              ∂                                  q                  n                                                            ∂                                  V                  1                                                                          ⋯                                                              ∂                                  q                  n                                                            ∂                                  V                  n                                                                        )        .  
For non-linear circuits, i.e., circuits including non-linear devices, SPICE often solves the circuit equations using the so-called Newton-Ralphson (N-R) iteration. To start the iteration process, SPICE selects an initial operating point for which the device model is evaluated. The initial operating point may include a set of terminal biases Vj(j=1, . . . , n) associated with each of a plurality of circuit elements. Based on the set of terminal biases for each of the circuit elements, SPICE evaluates the device models for modeling the circuit elements and produces model results such as terminal currents, node charges and the derivatives of the terminal currents and node charges (conductance and capacitance) associated with the circuit elements. SPICE then stamps the terminal currents, node charges, and their derivatives into designated entries in the matrices of the circuit equations. The process of obtaining model results and stamping the model results into matrices are often referred to as model evaluation and model stamping or matrix stamping. SPICE then solves the circuit equations to produce circuit voltages and currents based on the initial operating point. The circuit voltages and currents based on the initial guess of the operating point are used to generate a second operating point, and SPICE then iterates the above process to solve the circuit equations based on the second operating point. The iteration continues until the differences in circuit voltages and currents from two consecutive iteration rounds have fallen below some predetermined limits, and the solution is considered to have converged.
Thus, the correctness and the efficiency of circuit simulation depend on the correct implementation of the device models and correct stamping of the model results. For example, a basic requirement for the convergence of N-R iteration is the consistency between the terminal currents, node charges and their derivatives, which can be destroyed due to errors in the stamping of conductance or capacitance. As the technology advances and integrated circuits become more and more complex, it has become more and more difficult to guarantee the correct stamping of the model results. Usually, extensive model quality assurance (QA) procedures are followed after model evaluation to compare model results with golden data, which are obtained by measurements, by using a slower but more reliable simulation tool such as an electromagnetic field solver, or simply from a previous circuit simulation run. But this model QA method is disadvantageous because it depends on the quality of the golden data, which may be erroneous or simply unavailable, as in cases involving new technology and state-of-art device models.
Even when the golden data are available and reliable, conventional model QA procedures are still insufficient because the golden data are typically obtained by DC sweep of bias voltages and because conventional model QA procedures often use DC solution of the model equations for comparison with the golden data. As a result, conventional model QA procedures cannot detect errors in matrix stamping of conductance or capacitance entries because these errors have no effect on the accuracy of DC solutions. The errors in matrix stamping of conductance or capacitance entries will, however, affect the convergence and speed of the circuit simulation and should be detected before they are used to solve the circuit equations.
Furthermore, conventional model QA procedures are insufficient because they do not provide 100% bias coverage. The DC solution of the model equations and the comparison with golden data are usually performed for typical biases only. Moreover, conventional mode QA procedures do not test the consistency between currents, charges and their derivatives (conductance and capacitance), which is crucial for the convergence of N-R iteration.